Method and apparatus for scheduling out-of-order execution queue in out-of-order processor

ABSTRACT

The disclosure provides a method and an apparatus for scheduling an out-of-order execution queue in an out-of-order processor. The method includes: constructing a sequence maintenance queue with a same number of items as the out-of-order execution queue, and allocating an empty item for instructions and data entering the out-of-order execution queue, in which the sequence maintenance queue comprises at least one identity (id) field; numbering each item of the out-of-order execution queue sequentially, and recording an id number of each item of the out-of-order execution queue in the id field of the sequence maintenance queue; enabling the instructions to enter an item of the out-of-order execution queue corresponding to an id number pointed by a tail of the sequence maintenance queue; and selecting instructions in ready items for execution from the out-of-order execution queue according to id number information indicated by the sequence maintenance queue.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is the U.S. national phase application of InternationalApplication No. PCT/CN2021/095137, filed on May 21, 2021, which claimspriority to Chinese Patent Application No. 202010784534.3, filed on Oct.6, 2020, the entire contents of which are incorporated herein byreference.

TECHNICAL FIELD

The embodiments of the disclosure relate to the field of microprocessortechnology, in particular to a method and an apparatus for scheduling anout-of-order execution queue in an out-of-order processor.

BACKGROUND

The out-of-order execution queue in the out-of-order processor isconfigured to cache a certain number of instructions (where theinstruction can be a program instruction or internal operation(s)decoded internally by the processor, and an instruction may betranslated into one or more operations) and data. The processor isresponsible for allocating empty items for the instructions and data toenter into the queue, and selecting instructions and data that meetcertain conditions from the queue for execution. When the instructionsin the out-of-order processor enter into the out-of-order executionqueue, the instructions do not flow in the processor according to thesequence specified in the program. As long as execution conditions aremet, the following instructions can be first executed over the previousinstructions, so as to improve the instruction execution speed. Thehardware processing of the out-of-order execution queue is morecomplicated. Generally, its timing is on critical paths of theprocessor, which directly affects the frequency of the processor andconsumes more power and occupies large chip area. The out-of-orderexecution queue in the out-of-order processor includes issue queues,access queues for all levels of caches, miss-status handling registers(MSHR), and consistency request queues, etc. The out-of-order executionqueues need to maintain an execution sequence.

For instructions entering into the queue, it is necessary to allocateempty items that can be entered when there are multiple empty items.When the instructions in the queue are selected for execution, theinstructions that enter the queue first are firstly executed if multipleitems in the queue are ready (that is, an oldest-first strategy). Thisis because the older the instruction is, the more instructions arerelated to it. Therefore, the oldest instruction is first executed,which can effectively improve the degree of parallelism thatinstructions are executed by the processor. Furthermore, the hardwareresources of the processor are occupied by the oldest instruction,including other components such as other out-of-order execution queues,reorder buffers, and store buffers. The earlier these old instructionsare executed, the sooner these hardware resources can be released foruse of the following instructions. The sequence in which theinstructions enter into the queue is required for identifying whichinstructions are the oldest in the out-of-order execution queue. In amethod, the age of each instruction entering into the out-of-orderexecution queue is recorded in the queue. That is, a counter is used andeach item in the queue is sorted according to the counter. Thedisadvantage of this method is that, additional registers need to beadded for recording of the counter, there may be a register overflow,and the delay is also very large due to multi-level comparison andselection of the sorting circuit. In another common method, the sequenceof the instructions in the processor is recorded in a reorder buffer(ROB) and the sequence may be used for sorting. That is, a position ofeach instruction in the ROB is used as age information of theinstruction. The problem of this method is that, the ROB is essentiallya First Input First Output (FIFO) queue and the age information cannotbe expressed directly with its address, which needs to be transformed.The multi-level comparison of circuits is also a problem. In yet anothermethod, the sequence of the out-of-order execution queue is maintainedby pointers. The problem is that after each selection of instructionsand data for subsequent execution, a large amount of data movementsbetween the registers is required for maintaining the sequence, withhigh power consumption.

Therefore, there is a need to design low-latency, low-power, andsmall-area out-of-order execution queues in the out-of-order processor,so as to achieve concise and efficient allocation, selection andexecution for the entered instructions.

SUMMARY

According to a first aspect of the disclosure, a method for schedulingan out-of-order execution queue in an out-of-order processor includes:constructing a sequence maintenance queue with a same number of items asthe out-of-order execution queue, and allocating an empty item forinstructions and data entering the out-of-order execution queue, inwhich the sequence maintenance queue comprises at least one identity(id) field; numbering each item of the out-of-order execution queuesequentially, and recording an id number of each item of theout-of-order execution queue in the id field of the sequence maintenancequeue; enabling the instructions to enter an item of the out-of-orderexecution queue corresponding to an id number pointed by a tail of thesequence maintenance queue; and selecting instructions in ready itemsfor execution from the out-of-order execution queue according to idnumber information indicated by the sequence maintenance queue.

According to a second aspect of the disclosure provide an apparatus forscheduling an out-of-order execution queue in an out-of-order processor.The apparatus includes the processor and a memory configured to storecomputer instructions executable by the processor. The processor isconfigured to construct a sequence maintenance queue with a same numberof items as the out-of-order execution queue, and allocate empty itemsfor instructions and data entering the out-of-order execution queue, inwhich the sequence maintenance queue comprises at least one identity(id) field; number each item of the out-of-order execution queuesequentially, and record an id number of each item of the out-of-orderexecution queue in the id field of the sequence maintenance queue;enable the instructions to enter an item of the out-of-order executionqueue corresponding to an id number pointed by a tail of the sequencemaintenance queue; and select instructions in ready items for executionfrom the out-of-order execution queue according to id number informationindicated by the sequence maintenance queue.

According to a third aspect of the disclosure, a non-transitorycomputer-readable storage medium has a computer program stored thereon.When the computer program is executed by a processor, a method forscheduling an out-of-order execution queue in an out-of-order processoris implemented. The method includes: constructing a sequence maintenancequeue with a same number of items as the out-of-order execution queue,and allocating an empty item for instructions and data entering theout-of-order execution queue, in which the sequence maintenance queuecomprises at least one identity (id) field; numbering each item of theout-of-order execution queue sequentially, and recording an id number ofeach item of the out-of-order execution queue in the id field of thesequence maintenance queue; enabling the instructions to enter an itemof the out-of-order execution queue corresponding to an id numberpointed by a tail of the sequence maintenance queue; and selectinginstructions in ready items for execution from the out-of-orderexecution queue according to id number information indicated by thesequence maintenance queue.

Additional aspects and advantages of embodiments of the disclosure willbe given in part in the following descriptions, become apparent in partfrom the following descriptions, or be learned from the practice of theembodiments of the disclosure.

BRIEF DESCRIPTION OF THE DRAWINGS

The above and/or additional aspects and advantages of embodiments of thedisclosure will become apparent and more readily appreciated from thefollowing descriptions made with reference to the drawings, in which:

FIG. 1 is a flowchart of a method for scheduling an out-of-orderexecution queue in an out-of-order processor according to an embodimentof the disclosure.

FIG. 2 is a schematic diagram of initializing a sequence maintenancequeue and an out-of-order execution queue according to an embodiment ofthe disclosure.

FIG. 3 is a schematic diagram illustrating a process where theinstructions enter the item in the out-of-order execution queuecorresponding to the item with the id number 2 to which the tail of thesequence maintenance queue points according to an embodiment of thedisclosure.

FIG. 4 is a schematic diagram illustrating a process where a firstexecutable item is searched in an out-of-order execution queue forexecution according to an embodiment of the disclosure.

FIG. 5 is a schematic diagram illustrating a process for execution whenan out-of-order execution queue is full according to an embodiment ofthe disclosure.

FIG. 6 is a schematic diagram illustrating the instructions aresimultaneously executed and entered according to an embodiment of thedisclosure.

FIG. 7 is a schematic diagram illustrating there are empty items due tocancellation and no instruction enters the queue according to anembodiment of the disclosure.

FIG. 8 is a schematic diagram illustrating there are empty items due tocancellation and instructions enter the queue according to an embodimentof the disclosure.

FIG. 9 is a diagram of an apparatus for scheduling an out-of-orderexecution queue according to an embodiment of the disclosure.

FIG. 10 is a schematic diagram of initializing an issue queue accordingto an embodiment of the disclosure.

FIG. 11 is a schematic diagram illustrating a process where a dispatchedinstruction enters the 2^(nd) item of the issue queue pointed by thetail of the issue queue according to an embodiment of the disclosure.

FIG. 12 is a schematic diagram illustrating a process where a first item(i.e., the item 5) in the issue queue is searched for issuing that canbe issued according to an embodiment of the disclosure.

FIG. 13 is a schematic diagram illustrating an issuing process when theissue queue is full according to an embodiment of the disclosure.

FIG. 14 is a schematic diagram illustrating simultaneous issue anddispatch according to an embodiment of the disclosure.

FIG. 15 is a schematic diagram illustrating there are empty items due tocancellation without dispatching according to an embodiment of thedisclosure.

FIG. 16 is a schematic diagram illustrating there are empty items due tocancellation with dispatching according to an embodiment of thedisclosure.

FIG. 17 is an exemplary diagram of an apparatus for scheduling anout-of-order execution queue in an out-of-order processor according toan embodiment of the disclosure.

DETAILED DESCRIPTION

Embodiments of the disclosure will be described in detail and examplesof embodiments are illustrated in the drawings. The same or similarelements and the elements having the same or similar functions aredenoted by like reference numerals throughout the descriptions.Embodiments described herein with reference to drawings are explanatory,serve to explain the disclosure, and are not construed to limitembodiments of the disclosure.

The following describes a method and an apparatus for scheduling anout-of-order execution queue in an out-of-order processor according tothe embodiments of the disclosure with reference to the accompanyingdrawings.

In detail, FIG. 1 is a flowchart of a method for scheduling anout-of-order execution queue in an out-of-order processor according toan embodiment of the disclosure.

As illustrated in FIG. 1, the method for scheduling the out-of-orderexecution queue in the out-of-order processor includes the followingsteps.

At S101, a sequence maintenance queue with a same number of items as theout-of-order execution queue is constructed, and an empty item isallocated for instructions and data entering the out-of-order executionqueue, in which the sequence maintenance queue includes at least oneidentity id field.

The out-of-order execution queue includes one or more of a valid field,a ready (rdy) field and a data field, and the sequence maintenance queueincludes the id field.

In detail, the out-of-order execution queue includes information fieldsused by the instructions, such as a valid field, an rdy field, and adata field. The valid field for each item records whether the item isvalid (for example, defining the valid field being 1 means the item isvalid, and defining the valid field being 0 means the item is invalid).The rdy field for each item records whether the instructions and datafor the item are ready (for example, defining the rdy field being 1means that they are ready, i.e., reaching an executable state, anddefining the rdy field being 0 means they are not ready). The data fieldfor each item records information such as commands and data used for theinstructions of the item.

At S102, each item of the out-of-order execution queue is numberedsequentially, and an id number for each item of the out-of-orderexecution queue is recorded in the id field of the sequence maintenancequeue.

It may be understood that, the embodiments of the disclosure may usemultiple ways to number each item in the out-of-order execution queue.For example, n items in the out-of-order execution queue may besequentially numbered from 0 to n−1, the n items of the out-of-orderexecution queue may be also sequentially numbered from 1 to n, which isnot specifically limited here. Taking the numbers from 0 to n−1 as anexample, the id field of the sequence maintenance queue records the idnumber of each item in the out-of-order execution queue, which is usedto index each item in the out-of-order execution queue. That is, the idnumbers from 0 to n−1 correspond to 0 to n−1 items in the out-of-orderexecution queue.

In an embodiment of the disclosure, a first allocated item in theout-of-order execution queue next time is the item of the out-of-orderexecution queue corresponding to the id number pointed by the tail ofthe sequence maintenance queue.

It may be understood that, the content of the id number item in thesequence maintenance queue pointed by the tail of the sequencemaintenance queue is the first allocated item in the out-of-orderexecution queue, that is, the first empty item that may be allocated forthe entered instructions in the out-of-order execution queue.

At S103, the instructions are enabled to enter an item of theout-of-order execution queue corresponding to an id number pointed by atail of the sequence maintenance queue.

It may be understood that, the instructions are directly enabled withoutany search to enter into the item in the out-of-order execution queuecorresponding to the id number pointed by the tail of the sequencemaintenance queue, which is simple and efficient. The instructionselection for execution does not require multi-level comparison, withouta large amount of data movements and with low latency, saving powerconsumption and area.

At S104, instructions in ready items are selected from the out-of-orderexecution queue according to id number information indicated by thesequence maintenance queue.

It may be understood that in the embodiment of the disclosure, theinstructions that have been prepared for execution may be found from theout-of-order execution queue according to the id number informationindicated by the sequence maintenance queue. In addition, when there aremultiple instructions in the out-of-order execution queue that have beenalready prepared for execution, the embodiments of the disclosure mayfind the oldest instruction for execution from the out-of-orderexecution queue according to the id number information given by thesequence maintenance queue.

Furthermore, situations are respectively processed in the embodiments ofthe disclosure, such as, a situation where the processor performsinitialization, a situation where the instructions are only entered intothe out-of-order execution queue, a situation where the instructions areonly executed in the out-of-order execution queue, a situation where theinstructions are entered into the out-of-order execution queue andexecuted at the same time, a situation where cancellation occurs in theprocessor due to branch mis-prediction, speculative memory accesses failor exceptions, etc. The specific methods are as follows.

In an embodiment of the disclosure, when the processor performsinitialization, the method further includes: numbering the id field ofthe sequence maintenance queue sequentially from the top to the bottom,and setting the tail to 0, the valid field of each item in theout-of-order execution queue to 0, in which the valid field being 0indicates that the recorded item is invalid.

It may be understood that, during the initialization, the embodiments ofthe disclosure can use multiple ways to number the id fields. Forexample, the id fields of the sequence maintenance queue can be numberedfrom 0 to n−1 from the top to the bottom. For example, the items of theid field can also be numbered from 1 to n from the top to the bottom,and n is a positive integer, which is not specifically limited here.

The following embodiment will take as an example that the items of theid field from the top to the bottom are sequentially numbered from 0 ton−1. During the initialization, the id fields of the sequencemaintenance queue are sequentially set from 0 to n−1 and from the top tothe bottom, and tail is set to 0, the valid field of each item in theout-of-order execution queue is set to 0, as shown in FIG. 2.

In an embodiment of the disclosure, when the instructions are onlyentered into the out-of-order execution queue of the processor, themethod further includes: enabling the instructions to enter the item ofthe out-of-order execution queue corresponding to the id number pointedby the tail item of the sequence maintenance queue, and moving the tailof the sequence maintenance queue down by one item, where the tail inthe next cycle=the tail in the current cycle +1.

It may be understood that, when the instructions are only entered, theinstructions are enabled to enter the item of the out-of-order executionqueue corresponding to the id number pointed by the tail of the sequencemaintenance queue, where the tail in the next cycle=the tail in thecurrent cycle +1.

For example, FIG. 3 illustrates a process where the instructions areenabled to enter the item in the out-of-order execution queuecorresponding to the item with id number 2 pointed by the tail of thesequence maintenance queue. The item with id number 2 is set with avalid field being 1 and an rdy field being 1 which indicates theoperation for the entered instruction is ready. The data information forthe instructions are written into the data field of this item. The tailof the sequence maintenance queue in the next cycle moves to the nextitem and points to the item with id number 5.

Each time the entry for an instruction is received and no instruction isselected for execution in the same cycle, the tail of the sequencemaintenance queue moves down by one item. When the out-of-orderexecution queue is full, the tail of the sequence maintenance queue=n.

In an embodiment of the disclosure, when the instructions are onlyexecuted in the out-of-order execution queue of the processor, themethod also includes: in an order from the top to the bottom, up to thetail item in the sequence maintenance queue, searching a first itemwhose valid field is 1 and rdy field is 1 for execution from the itemsin the out-of-order execution queue, setting the executed first item tobe an empty item, moving the contents in the tail item and items beforethe tail item up by one item and saving an id number corresponding tothe empty item in the id field of the tail item of the sequencemaintenance queue, where the tail in the next cycle=the tail in thecurrent cycle −1, the valid field being 1 indicates that the recordeditem is valid, and the rdy field being 1 indicates that the instructionsand data of the recorded item are ready.

It may be understood that, when the instructions are only executed, thesequence maintenance queue finds out the first item in the out-of-orderexecution queue that corresponds to the id number and satisfies valid==1and rdy==1 for execution, from the top to the bottom, up to the tail,the contents in the tail of the sequence maintenance queue and itsprevious items (together with the tail) are moved up by one item, the idnumber corresponding to the item in the out-of-order execution queueselected for execution and vacated is saved in the id field of the tailitem of the sequence maintenance queue, where the tail in the nextcycle=the tail in the current cycle −1.

For example, FIG. 4 illustrates a process where a first executable item(i.e., the item with the id number 5) is searched in the out-of-orderexecution queue for execution. After the execution, the valid of theitem 5 in the out-of-order execution queue is set to 0, and the idnumbers n−1, 0, and 2 in the items of the sequence maintenance queue areall moved up by one item, and the id number 5 corresponding to the itemin the out-of-order execution queue that is selected for execution issaved to the item pointed by the tail of the sequence maintenance queue.In the next cycle, the tail is moved up by one item, that is, the tailpoints to the item with the id number 2.

In particular, when the tail of the sequence maintenance queue==n, (thatis, when the out-of-order execution queue is full), after the readyinstructions are executed, the contents in the items before the tail aremoved up by one item, and the id number in the empty item afterexecution do not enter into the tail item, but the (tail−1) item, andthe tail in the next cycle=n−1.

In FIG. 5, when the out-of-order execution queue is full (that is,tail==n), the item with the id number 2 in the sequence maintenancequeue is selected from the top to the bottom, that is, the instructionfor the 2^(nd) item in the out-of-order execution queue is issued. Theid numbers 3, 6, . . . , 4 in the items of the sequence maintenancequeue are moved up, the id number 2 of the execution item is writteninto the (tail−1) item of the sequence maintenance queue, which is the(n−1) item, where the tail in the next cycle=n−1.

In an embodiment of the disclosure, when the instructions in theout-of-order execution queue of the processor are entered and executedat the same time, the method further includes: enabling a newinstruction to enter the item in the out-of-sequence execution queuecorresponding to the id number pointed by the tail of the sequencemaintenance queue, moving the id number in each item of the sequencemaintenance queue up by one item, and storing the id number of the issueitem into the tail item, wherein the value of the tail in the next cycleremains unchanged.

It may be understood that, when the instructions are executed andentered at the same time in one cycle, the new instruction enters theitem of the out-of-sequence execution queue corresponding to the idnumber pointed by the tail item of the sequence maintenance queue, theid numbers in the tail item and items before the tail item (as well asthe tail) are all moved up by one item, the id corresponding to theissue item is stored in the tail item, and the value of tail in the nextcycle remains unchanged.

For example, FIG. 6 illustrates a process where the instruction entersthe 5^(th) item in the out-of-order execution queue corresponding to thetail, and the instruction for the (n−1)^(th) item in the out-of-orderexecution queue is selected from the top to the tail is issued. For the5^(th) item in the issue queue, its valid is set to 1 and its rdy fordetermining whether the operation of the dispatched instruction is readyor not is set to 0, indicating the operation is not ready. Theinstruction and data information are written into the data field. The idnumbers 0, 2, and 5 in the items of the sequence maintenance queue aremoved up by one item at the same time, and the id number (n−1) for theissue item is stored to the item pointed by the tail.

In an embodiment of the disclosure, when the processor is in acancellation situation, the method further includes: setting the validof a cancelled item in the out-of-order execution queue to 0, in whichthe cancelled item whose valid is set to 0 is an empty item, and no newinstruction enters the cancelled item, and a value of the tail of thesequence execution queue remains unchanged.

The cancellation situations include a variety of situations, forexample, branch mis-prediction, speculative memory accesses fail orexceptions, etc., which is not limited here.

It may be understood that when the processor enables some items in theout-of-order execution queue to be cancelled due to branchmis-prediction, speculative memory accesses fail or exceptions, thevalid of each cancelled item in the out-of-order execution queue is setto 0, no new instructions may be entered for this cancellation cycle,and the tail of the sequence maintenance queue remains unchanged.

When there are empty items in the out-of-order execution queuecorresponding to the id numbers before the tail item of the sequencemaintenance queue due to the cancellation. That is, the out-of-orderexecution queue has items with valid==0, the following processes isperformed for each case.

(1) In an embodiment of the disclosure, if there is no instruction to beexecuted or entered in the current cycle, the following is performedaccording to a first preset situation, where only one empty item isprocessed in one cycle, and the first empty item is searchedsequentially from the top to the tail item in the sequence maintenancequeue, the contents in the tail item and items before the tail item aremoved up by one item, the id number corresponding to the first emptyitem is stored in the tail item, where the tail in the next cycle=thetail in the current cycle −1.

The first preset situation may be a situation that the instruction isonly executed or otherwise, which are not specifically limited here.Taking the first preset situation where the instruction is only executedas an example, it may be understood that if there is no instruction tobe executed or entered in the current cycle, the empty items areprocessed in the same way as the item for which the instruction is onlyexecuted and only one empty item is processed in one cycle. That is, thefirst empty item is selected from the top to the tail item, the contentsin the tail item and its previous items (together with the tail) aremoved up by one item, the id corresponding to the empty item is storedin the tail item, where the tail in the next cycle=the tail in thecurrent cycle −1.

In FIG. 7, the (n−1)^(th), 0, and 2 items of the out-of-order executionqueue are canceled due to branch cancellation, the valid of thecorresponding item in the out-of-order execution queue is 0, and noinstruction enters in the current cycle. The out-of-order executionqueue is searched through the sequence maintenance queue from the top tothe tail according to the id, so as to determine the first empty item,i.e., the (n−1)^(th) item. Then, the id numbers 0, 2, and 3 are moved upby one item respectively, and the id number n−1 for the empty item isstored in the item pointed by the tail. The tail is moved up by one itemin the next cycle and points to the item with the id number 3.

(2) In an embodiment of the disclosure, if there is no instruction to beexecuted in the current cycle while there is an instruction to beentered, the following is performed according to a second presetsituation where one empty item is processed in one cycle, the newinstruction enters the item in the out-of-order execution queuecorresponding to the id number for the tail item, and the first emptyitem is searched from the top to the tail item, the id numbers in thetail item and the items before the tail item are moved up by one item,the id number for the first empty item is stored in the tail item, and avalue of the tail in the next cycle remains unchanged.

The second preset situation may be a situation in which instructions areentered and are executed at the same time or otherwise, which is notspecifically limited here. Taking the second preset situation where theinstructions are entered and are executed at the same time as anexample, it can be understood that if there is no instruction to beexecuted in the current cycle, and there is instruction to be entered inthe current cycle, then the empty item is processed as an execution itemin the same way that there are instruction execution items andinstruction entering items at the same time in the same cycle. Only oneempty item is processed in one cycle. The new instruction enters theitem in the out-of-order execution queue corresponding to the id pointedby the tail. The first empty item is searched from the top to the tailitem, and the id numbers in the tail item and its previous items(together with the tail) are moved up by one item, and the id for theempty item is stored in the tail item, and a value of tail remainsunchanged in the next cycle.

In FIG. 8, the (n−1)^(th), 0, and 2 items of the out-of-order executionqueue are cancelled due to branch cancellation, the valid of thecorresponding item in the out-of-order execution queue is 0, and aninstruction enters in the current cycle. The instruction enters the3^(rd) item corresponding to the content pointed to by the tail. For the3^(rd) item in the out-of-order execution queue, its valid is set to 1,and its rdy for determining whether the dispatched instruction is readyor not is set to 0, indicating the operating condition of thisinstruction is not ready. From the top to the tail item, the first emptyitems is searched, i.e., the (n−1)^(th) item. The id numbers 0, 2, and 3in the items of the sequence maintenance queue are all moved up by oneitem. The id number (n−1) for the empty item is stored in the itempointed by the tail, and the tail remains unchanged in the next cycle,pointing to the item with the id number (n−1).

(3) In an embodiment of the disclosure, if the queue is full, thefollowing is performed according to a third preset situation, where anempty item may be processed in the current cycle, and the contents inthe items of the sequence maintenance queue may be moved up by one item.The id number corresponding to the empty item enters the (tail−1) item,where the tail in the next cycle=the last item of the sequencemaintenance queue.

The third preset situation may be a situation where instructions areonly executed. Taking the third preset situation where instructions areonly executed as an example, it can be understood that if tail==n, theprocessing on a situation where an empty item appears in theout-of-order execution queue due to cancellation is the same as theprocessing on a situation where there are only execution items in thecurrent cycle, in which only one empty item is processed in one cycle.The content in each item before the tail is moved up by one item, the idnumber corresponding to the empty item does not enter the tail item, butenters the (tail−1) item, where the tail in the next cycle=n−1.

Further, the apparatus configured to execute the method for schedulingan out-of-order execution queue in an out-of-order processor is shown inFIG. 9. The distribution circuit is configured to find out the emptyitems in the out-of-order execution queue and enable the entered newinstructions to be stored in the empty items. The arbitration circuit isalso called the selection circuit. When multiple instructions in theout-of-order execution queue are ready to be executed, the oldestinstruction is selected from the out-of-order execution queue forexecution according to the id number information given by a sequencemaintenance circuit.

When the instructions are entered, the distribution circuit selectsempty items for entering. The item in the out-of-order execution queueis selected for entering according to the content in the id fieldpointed by the tail of the sequence maintenance queue. When theinstructions are selected for execution, the arbitration circuit selectsthe oldest item (which has been already prepared for execution) in theout-of-sequence execution queue for execution according to the id numberinformation given by the sequence maintenance queue by using theabove-mentioned scheduling method. According to the correspondingoperation, the tail and the id field content of the sequence maintenancequeue are operated accordingly.

It should be noted that the out-of-order execution queue may includeissue queues, access queues for all levels of caches, queues inmiss-status handling registers (MSHR), and consistency request queues,etc. All the out-of-order execution queues in the processor can use thescheduling method according to the embodiments of the disclosure, whichimplements concise and efficient allocation of instruction entering andselection of instruction executing.

The following will further describe the method for scheduling anout-of-order execution queue in an out-of-order processor in theembodiments in which the issue queue is used as the out-of-orderexecution queue.

In detail, the number of items in the issue queue of the processor inthe embodiment is set to 8. The function of the issue queue is to selectthose instructions that have been prepared for the source operands, andissue those instructions to a function unit (FU) for execution. Thisprocess is called issuing. After the instruction enters the issue queue,it will no longer flow in the processor according to the sequencespecified in the program. As long as the operand of an instruction inthe issue queue is ready and the issuing conditions are met, theinstruction can be issued to execute in the corresponding function unit.The instruction input by the issue queue comes from the instructiondispatched by a register renaming module. The oldest instruction whoseoperand has been prepared is selected and issued to the function unitfor execution.

An issue sequence maintenance queue with the same number of items as theissue queue is constructed, that is, 8 items, which are used to allocateempty items for the dispatched instructions to enter and select itemsfrom the issue queue that are issued to the function units forexecution.

The id field of the issue sequence maintenance queue records the idnumber corresponding to the item of the issue queue. A first allocateditem in the issue queue next time is the item of the issue queuecorresponding to the id number pointed by the tail of the issue sequencemaintenance queue.

The valid field of the issue queue records whether the item is valid,the rdy field records whether the operand is ready, and the data fieldrecords information such as the function unit and source operandcorresponding to the instruction.

The situations are respectively processed, such as, a situation wherethe processor performs initialization, a situation where the issue queueonly performs dispatching, a situation where the issue queue onlyperforms issuing, a situation where the issue queue simultaneouslyperform dispatching and issuing, a situation where the processorperforms cancellation.

1. Initialization

During the initialization, the id numbers of items numbered 0 to 7 ofthe issue sequence maintenance queue are set to 0-7, the tail is set to0, and the valid of each item in the issue queue is set to 0, as shownin FIG. 10.

2. Only Dispatching

The new instructions are dispatched to enter the item of the issue queuepointed by the id for the tail item of the issue sequence maintenancequeue, where the tail in the next cycle=the tail in the current cycle+1.

FIG. 11 illustrates a process where the instruction is dispatched toenter the 2^(nd) item of the issue queue pointed by the tail of theissue queue, the valid of the 2^(nd) item of the issue queue is set to1, its rdy is set to 1, which indicates that the operand for thedispatched instruction is ready, and instruction and operand informationof each dispatched instruction are written into the data field, in whichthe tail of the sequence maintenance queue in the next cycle is moved tothe next item, pointing to the item with the id number 5.

Each time the dispatching of an instruction is received and issuing isnot performed in the same cycle, the tail of the issue sequencemaintenance queue moves down by one item. When the issue queue is full,the tail of the issue sequence maintenance queue is equal to 8.

3. Only Issuing

The first item corresponding to the id number of the issue sequencemaintenance queue that satisfies valid==1 and rdy==1 is searched in theissue queue from the top to the bottom to the tail, and is issued to thefunction unit, and the contents in the tail item and its previous items(together with the tail) of the issue sequence maintenance queue aremoved up by one item, and the id corresponding to the issue item afterissuing is stored in the tail item, where the tail in the next cycle=thetail in the current cycle −1.

FIG. 12 illustrates a process where a first item (i.e., the item 5) inthe issue queue is searched for issuing that can be issued. The valid ofthe issue item 5 of the issue queue is set to 0, the id numbers 7, 0,and 2 in the items of the issue sequence maintenance queue are all movedup by one item, and the id number 5 corresponding to the issue item isstored in the item pointed by the tail. The tail in the next cycle ismoved up by one item, i.e., pointing to the item with the id number 2.

When the tail of the issue sequence maintenance queue points to 8, thatis, the issue queue is full, the contents in items before the tail aremoved up by one item after the instructions with ready operands areissued, the id number corresponding to the issue item does not enter thetail item, but enters the tail−1 item. The tail in the next cycle=7.

In FIG. 13, tail==8 (i.e., when the issue queue is full), the item withthe id number 2 of the issue sequence maintenance queue is selected fromthe top to the bottom, and the instruction for the 2^(nd) item in theissue queue is issued. The id numbers 3, 6 and 4 in the items of theissue sequence maintenance queue are moved up, the id number 2 for theissue item is written into the (tail−1) item (i.e., the 7^(th) item) ofthe issue sequence maintenance queue, where the tail in the nextcycle=7.

4. Dispatching and Issuing in One Cycle

If issuing and dispatching occur at the same time, the newly dispatchedinstruction enters an issue queue item corresponding to the id numberpointed by the tail of the issue sequence maintenance queue. The idnumbers in the tail item and its previous items (together with the tail)are moved up by one item. The id for the issue item is stored in thetail item, and a value of the tail remains unchanged in the next cycle.

FIG. 14 illustrates a process where the dispatched instruction entersthe 5^(th) item of the issue queue corresponding to the tail content,and the 7^(th) item of the issue queue is selected from the top to thetail for issuing. The valid of the 5^(th) item of the issue queue is setto 1, rdy is set to 0, which indicates that the operand of thedispatched instruction is not ready, and instruction and operandinformation of each dispatched instruction is written into the datafield. The contents 0, 2, and 5 in the items of the issue sequencemaintenance queue are moved up by one item at the same time, and the idnumber 7 for the issue item is stored in the item pointed by the tailitem.

5. Cancellation

When the cancellation occurs, the valid of the cancelled item in theissue queue is set to 0, and no new instructions may be dispatched forentering in the cancelling cycle, and the tail value of the issuesequence maintenance queue remains unchanged.

When there are empty items in the issue queue corresponding to the id ofthe issue sequence maintenance queue before the tail due tocancellation, that is, the issue queue has items with valid==0, thefollowing is performed according to the situation.

(1) If there is no instruction to be issued or dispatched in the currentcycle, the empty items are processed by the issue sequence maintenancequeue in a same way as a situation where there are only issue items andonly one empty item may be processed in one cycle. The first empty itemis found from the top to the tail item, and the contents in the tailitem and its previous items (including the tail) are moved up by oneitem, the id corresponding to the empty item is stored in the tail item,where the tail in the next cycle=the tail in the current cycle −1.

FIG. 15 shows that the items 7, 0, and 2 in the issue queue arecancelled due to branch cancellation. The valid bit of the correspondingitem in the issue queue is 0, and there is no instruction dispatched inthis cycle. The first empty item (the 7^(th) item) in the issue queue isfound according to the id numbers of the issue sequence maintenancequeue from the top to the tail item. The id numbers 0, 2, and 3 aremoved up by one item respectively, and the id number 7 for the emptyitem is stored in the item pointed by the tail, the tail in the nextcycle is moved up by one item, pointing to the item with the id number3.

(2) If there is an instruction to be issued and to be dispatched in thecurrent cycle, the empty item may be treated as an issue item and beprocessed in a same way as a situation where there are issue anddispatch items in the same cycle, and only one empty item may beprocessed in one cycle. The newly dispatched instruction enters the itemin the issue queue corresponding to the id of the tail item. The firstempty item is found from the top to the tail item. The id numbers in thetail item and its previous items (including the tail) are moved up byone item. The id for the empty item is stored in the tail item, and thevalue of tail remains unchanged in the next cycle.

FIG. 16 shows that the items 7, 0, and 2 in the issue queue arecancelled due to branch cancellation. The valid bit of the correspondingitem in the issue queue is 0, and there is an instruction dispatched inthis cycle. The dispatched instruction enters the 3^(rd) itemcorresponding to the content pointed by the tail. The valid of the3^(rd) item of the issue queue is set to 1, and the rdy is set to 0,which indicates that the operand of the dispatched instruction is notready. The first empty item (the 7^(th) item) in the issue queue isfound from the top to the tail item. The id numbers 0, 2, and 3 aremoved up by one item respectively, and the id number 7 for the emptyitem is stored in the item pointed by the tail, the tail in the nextcycle remains unchanged in the next cycle, pointing to the item with theid number 7.

(3) If tail==8, the processing when there is an empty item in the issuequeue due to cancellation is the same as the processing when there isonly issue items in this cycle, and only one empty item is processed inone cycle. The contents in items before the tail item are moved up byone item, the id corresponding to the empty item does not enter the tailitem, but enters the (tail−1) item, where the tail in the next cycle=7.

According to the method for scheduling the out-of-order execution queuein the out-of-order processor of the embodiments of the disclosure, thesequence maintenance queue is used to maintain the sequence of theout-of-order execution queue, to improve scheduling efficiency, reducescheduling complexity, and achieve low power consumption, low latency,and save area, further to improve processor performance and reducecosts.

Next, the apparatus for scheduling the out-of-order execution queue inthe out-of-order processor according to the embodiments of thedisclosure will be described with reference to the accompanyingdrawings.

FIG. 17 is a schematic diagram of an apparatus for scheduling anout-of-order execution queue in an out-of-order processor according toan embodiment of the disclosure.

As illustrated in FIG. 17, the apparatus 10 for scheduling theout-of-order execution queue of the out-of-order processor includes: aconstructing module 100, a numbering module 200, an entering module 300and a selecting module 400.

The constructing module 100 is configured to construct a sequencemaintenance queue with a same number of items as the out-of-orderexecution queue, and allocate an empty item for instructions and dataentering the out-of-order execution queue, wherein the sequencemaintenance queue comprises at least one identity (id) field. Thenumbering module 200 is configured to number each item of theout-of-order execution queue sequentially, and record an id number ofeach item of the out-of-order execution queue in the id field of thesequence maintenance queue. The entering module 300 is configured toenable the instructions to enter an item of the out-of-order executionqueue corresponding to an id number pointed by a tail of the sequencemaintenance queue. The selecting module 400 is configured to selectinstructions in ready items for execution from the out-of-orderexecution queue according to id number information indicated by thesequence maintenance queue.

It should be noted that the foregoing explanation of the method forscheduling an out-of-order execution queue in an out-of-order processoris also applicable to the apparatus for scheduling an out-of-orderexecution queue in an out-of-order processor in this embodiment, andwhich will not be repeated here.

With the apparatus for scheduling an out-of-order execution queue in anout-of-order processor according to the embodiments of the disclosure,the sequence maintenance queue is used to maintain the sequence of theout-of-order execution queue, in order to improve scheduling efficiencyand reduce scheduling complexity, and to achieve low power consumption,low delay, and to save area, further to improve processor performance,increase main frequency, reduce power consumption and costs.

The embodiments of the disclosure further provide an electronic device,the electronic device includes at least one processor and a memorycommunicatively connected with the at least one processor. The memorystores instructions that can be executed by the at least one processor.When the instructions are executed, the method for scheduling anout-of-order execution queue in an out-of-order processor according tothe above embodiments is implemented.

The embodiments of the disclosure also provide a computer-readablestorage medium on which a computer program is stored, when the programis executed by the processor, the method for scheduling an out-of-orderexecution queue in an out-of-order processor as described above isimplemented.

Reference throughout this specification to “an embodiment,” “someembodiments,” “an example,” “a specific example,” or “some examples,”means that a particular feature, structure, material, or characteristicdescribed in connection with the embodiment or example is included in atleast one embodiment or example of the disclosure. The appearances ofthe above phrases in various places throughout this specification arenot necessarily referring to the same embodiment or example of thedisclosure. Furthermore, the particular features, structures, materials,or characteristics may be combined in any suitable manner in one or Nembodiments or examples. In addition, different embodiments or examplesand features of different embodiments or examples described in thespecification may be combined by those skilled in the art without mutualcontradiction.

In addition, terms such as “first” and “second” are used herein forpurposes of description and are not intended to indicate or implyrelative importance or significance. Thus, the feature defined with“first” and “second” may comprise one or more this feature. In thedescription of the disclosure, “N” means at least two, for example, twoor three, unless specified otherwise.

Any process or method described in a flowchart or described herein inother ways may be understood to include one or N modules, segments orportions of codes of executable instructions for achieving specificlogical functions or steps in the process, and the scope of a preferredembodiment of the disclosure includes other implementations, whichshould be understood by those skilled in the art.

The logic and/or step described in other manners herein or shown in theflow chart, for example, a particular sequence table of executableinstructions for realizing the logical function, may be specificallyachieved in any computer readable medium to be used by the instructionexecution system, device or equipment (such as the system based oncomputers, the system comprising processors or other systems capable ofobtaining the instruction from the instruction execution system, deviceand equipment and executing the instruction), or to be used incombination with the instruction execution system, device and equipment.As to the specification, “the computer readable medium” may be anydevice adaptive for including, storing, communicating, propagating ortransferring programs to be used by or in combination with theinstruction execution system, device or equipment. More specificexamples of the computer readable medium comprise but are not limitedto: an electronic connection (an electronic device) with one or N wires,a portable computer enclosure (a magnetic device), a random accessmemory (RAM), a read only memory (ROM), an erasable programmableread-only memory (EPROM or a flash memory), an optical fiber device anda portable compact disk read-only memory (CDROM). In addition, thecomputer readable medium may even be a paper or other appropriate mediumcapable of printing programs thereon, this is because, for example, thepaper or other appropriate medium may be optically scanned and thenedited, decrypted or processed with other appropriate methods whennecessary to obtain the programs in an electric manner, and then theprograms may be stored in the computer memories.

It should be understood that each part of the disclosure may be realizedby the hardware, software, firmware or their combination. In the aboveembodiments, N steps or methods may be realized by the software orfirmware stored in the memory and executed by the appropriateinstruction execution system. For example, if it is realized by thehardware, likewise in another embodiment, the steps or methods may berealized by one or a combination of the following techniques known inthe art: discrete logic circuits having logic gate circuits forrealizing a logic function of a data signal, an application-specificintegrated circuit having an appropriate combination logic gate circuit,a programmable gate array (PGA), a field programmable gate array (FPGA),etc.

It would be understood by those skilled in the art that all or a part ofthe steps carried by the method in the above-described embodiments maybe completed by relevant hardware instructed by a program. The programmay be stored in a computer readable storage medium. When the program isexecuted, one or a combination of the steps of the method in theabove-described embodiments may be completed.

In addition, individual function units in the embodiments of thedisclosure may be integrated in one processing module or may beseparately physically present, or two or more units may be integrated inone module. The integrated module as described above may be achieved inthe form of hardware, or may be achieved in the form of a softwarefunctional module. If the integrated module is achieved in the form of asoftware functional module and sold or used as a separate product, theintegrated module may also be stored in a computer readable storagemedium.

The storage medium mentioned above may be read-only memories, magneticdisks or CD, etc. Although explanatory embodiments have been shown anddescribed, it would be appreciated by those skilled in the art that theabove embodiments cannot be construed to limit the disclosure, andchanges, alternatives, and modifications can be made in the embodimentswithout departing from scope of the disclosure.

1. A method for scheduling an out-of-order execution queue in anout-of-order processor, comprising: constructing a sequence maintenancequeue with a same number of items as the out-of-order execution queue,and allocating an empty item for instructions and data entering theout-of-order execution queue, wherein the sequence maintenance queuecomprises at least one identity (id) field; numbering each item of theout-of-order execution queue sequentially, and recording an id number ofeach item of the out-of-order execution queue in the id field of thesequence maintenance queue; enabling the instructions to enter an itemof the out-of-order execution queue corresponding to an id numberpointed by a tail of the sequence maintenance queue; and selectinginstructions in ready items for execution from the out-of-orderexecution queue according to id number information indicated by thesequence maintenance queue.
 2. The method according to claim 1, whereina first allocated item in the out-of-order execution queue next time isthe item of the out-of-order execution queue corresponding to the idnumber pointed by the tail of the sequence maintenance queue.
 3. Themethod according to claim 1, wherein each item in the out-of-orderexecution queue comprises a valid field and a ready (rdy) field, inwhich the valid field is configured to record whether the item of theout-of-order execution queue is valid, the rdy field is configured torecord whether the instructions and data in the item of the out-of-orderexecution queue are ready, and the sequence maintenance queue comprisesa tail item, in which the tail item is an item pointed by the tail ofthe sequence maintenance queue.
 4. The method according to claim 3, whenthe processor performs initialization, the method further comprises:numbering the id field of each item in the sequence maintenance queuesequentially from the top to the bottom, and setting the tail to 0, thevalid field of each item in the out-of-order execution queue to 0, inwhich the valid field being 0 indicates that the recorded item isinvalid.
 5. The method according to claim 1, wherein when theinstructions are only entered into the out-of-order execution queue ofthe processor, the method further comprises: enabling the instructionsto enter the item of the out-of-order execution queue corresponding tothe id number pointed by the tail and moving the tail down by one item,where the tail in the next cycle=the tail in the current cycle +1. 6.The method according to claim 3, wherein when the instructions are onlyexecuted in the out-of-order execution queue of the processor, themethod further comprises: in an order from the top to the tail item inthe sequence maintenance queue, searching a first item whose valid fieldis 1 and rdy field is 1 from the items in the out-of-order executionqueue and executing an instruction for the first item, setting theexecuted first item to be an empty item, moving the id number in thetail item and the id number in items between the tail item and the emptyitem up by one item, and saving an id number corresponding to the emptyitem in the id field of the tail item, where the tail in the nextcycle=the tail in the current cycle −1, the valid field being 1indicates that the recorded item is valid, and the rdy field being 1indicates that the instructions and data of the recorded item are ready.7. The method according to claim 6, wherein when the queue is full, themethod further comprises: after the ready instructions are executed,moving the id numbers in the items between the tail item and the emptyitem up by one item, enabling the empty item whose instructions areexecuted in the out-of-order execution queue into a (tail−1) item, inwhich the (tail−1) item is the last item of the sequence maintenancequeue in the current cycle, and enabling the tail in the next cycle topoint to the last item of the sequence maintenance queue in the currentcycle, where the tail in the next cycle=the number of the last item ofthe sequence maintenance queue in the current cycle.
 8. The methodaccording to claim 3, wherein when the instructions are entered into theout-of-order execution queue of the processor and executed at the sametime, the method further comprises: enabling new instructions to enterinto the item of the out-of-sequence execution queue corresponding tothe id number pointed by the tail, moving the id number in the tail itemand the id number in each item between the tail item and an issuing itemup by one item, wherein the issuing item is a first item whose validfield is 1 and rdy field is 1 in an order from the top to the tail item,and storing an id number for the issuing item in the tail item, whereinthe tail in the next cycle remains unchanged.
 9. The method according toclaim 3, wherein when the processor is in a cancellation situation, themethod further comprises: setting the valid field of a cancelled item inthe out-of-order execution queue to 0, wherein the cancelled item whosevalid field is set to 0 is an empty item, and no new instructions areentered into the cancelled item, and the tail remains unchanged.
 10. Themethod according to claim 9, wherein when there are no instructionsexecuted or entered in the current cycle, the items are processedaccording to a first preset situation, where only one empty item isprocessed in one cycle, and a first empty item is searched sequentiallyfrom the top to the tail item, the id number in the tail item and the idnumbers in items between the tail item and the first empty item aremoved up by one item, the id number corresponding to the first emptyitem is stored in the tail item, where the tail in the next cycle=thetail in the current cycle −1.
 11. The method according to claim 9,wherein when there are no instructions executed in the current cycle,and there are new instructions entered in the current cycle, the itemsare processed according to a second preset situation, where one emptyitem is processed in one cycle, the new instructions are entered intothe item of the out-of-order execution queue corresponding to the idnumber for the tail item, and a first empty item is searched from thetop to the tail item, the id number in the tail item and the id numberin items between the tail item and the first empty item are moved up byone item, the id number for the first empty item is stored in the tailitem, and the tail in the next cycle remains unchanged.
 12. The methodaccording to claim 9, wherein when the queue is full, the items areprocessed according to a third preset situation, where one empty item isprocessed in the current cycle, the id number in each item between thetail item and the empty item is moved up by one item, and the id numbercorresponding to the empty item are entered into the (tail−1) item inwhich the (tail-1) item is the last item of the sequence maintenancequeue in the current cycle, the tail in the next cycle points to thelast item of the sequence maintenance queue in the current cycle, wherethe tail in the next cycle=the number of the last item of the sequencemaintenance queue in the current cycle.
 13. An apparatus for schedulingan out-of-order execution queue in an out-of-order processor,comprising: the processor; and a memory configured to store computerinstructions executable by the processor; module, wherein the processoris configured to: construct a sequence maintenance queue with a samenumber of items as the out-of-order execution queue, and allocate emptyitems for instructions and data entering the out-of-order executionqueue, wherein the sequence maintenance queue comprises at least oneidentity (id) field; number each item of the out-of-order executionqueue sequentially, and record an id number of each item of theout-of-order execution queue in the id field of the sequence maintenancequeue; enable the instructions to enter an item of the out-of-orderexecution queue corresponding to an id number pointed by a tail of thesequence maintenance queue; and select instructions in ready items forexecution from the out-of-order execution queue according to id numberinformation indicated by the sequence maintenance queue.
 14. (canceled)15. A non-transitory computer-readable storage medium having a computerprogram stored thereon, wherein when the computer program is executed bya processor, a method for scheduling an out-of-order execution queue inan out-of-order processor is implemented, the method comprising:constructing a sequence maintenance queue with a same number of items asthe out-of-order execution queue, and allocating an empty item forinstructions and data entering the out-of-order execution queue, whereinthe sequence maintenance queue comprises at least one identity (id)field; numbering each item of the out-of-order execution queuesequentially, and recording an id number of each item of theout-of-order execution queue in the id field of the sequence maintenancequeue; enabling the instructions to enter an item of the out-of-orderexecution queue corresponding to an id number pointed by a tail of thesequence maintenance queue; and selecting instructions in ready itemsfor execution from the out-of-order execution queue according to idnumber information indicated by the sequence maintenance queue.
 16. Theapparatus according to claim 13, wherein each item in the out-of-orderexecution queue comprises a valid field and a ready (rdy) field, inwhich the valid field is configured to record whether the item of theout-of-order execution queue is valid, the rdy field is configured torecord whether the instructions and data in the item of the out-of-orderexecution queue are ready, and the sequence maintenance queue comprisesa tail item, in which the tail item is an item pointed by the tail ofthe sequence maintenance queue.
 17. The apparatus according to claim 16,wherein when the processor performs initialization, the processor isfurther configured to: number the id field of each item in the sequencemaintenance queue sequentially from the top to the bottom, and set thetail item to 0, the valid field of each item in the out-of-orderexecution queue to 0, in which the valid field being 0 indicates thatthe recorded item is invalid.
 18. The apparatus according to claim 13,wherein when the instructions are only entered into the out-of-orderexecution queue, the processor is further configured to: enable theinstructions to enter the item of the out-of-order execution queuecorresponding to the id number pointed by the tail, and moving the taildown by one item, where the tail in the next cycle=the tail in thecurrent cycle +1.
 19. The apparatus according to claim 16, wherein whenthe instructions are only executed in the out-of-order execution queue,the processor is further configured to: search a first item whose validfield is 1 and rdy field is 1 for execution from the items in theout-of-order execution queue in an order from the top to the tail itemin the sequence maintenance queue, set the executed first item to be anempty item, move the id number in the tail item and the id number initems between the tail item and the empty item up by one item, and savean id number corresponding to the empty item in the id field of the tailitem, where the tail in the next cycle=the tail in the current cycle −1,the valid field being 1 indicates that the recorded item is valid, andthe rdy field being 1 indicates that the instructions and data of therecorded item are ready.
 20. The apparatus according to claim 19,wherein when the queue is full, the processor is further configured to:after the ready instructions are executed, move the id numbers in theitems between the tail item and the empty item up by one item, enablethe empty item whose instructions are executed in the out-of-orderexecution queue into a (tail−1) item, in which the (tail−1) item is thelast item of the sequence maintenance queue in the current cycle, andenable the tail in the next cycle to point to the last item of thesequence maintenance queue in the current cycle, where the tail in thenext cycle=the number of the last item of the sequence maintenance queuein the current cycle.
 21. The apparatus according to claim 16, whereinwhen the instructions are entered into the out-of-order execution queueand executed at the same time, the processor is further configured to:enable new instructions to enter into the item of the out-of-sequenceexecution queue corresponding to the id number pointed by the tail,moving the id number in the tail item and the id number in each itembetween the tail item and an issuing item up by one item, wherein theissuing item is a first item whose valid field is 1 and rdy field is 1in an order from the top to the tail item, and storing an id number forthe issuing item in the tail item, wherein the tail in the next cycleremains unchanged.